Service Description

Part 1, Verilog Learning Course Outline: • Introduction to FPGAs - What it is. - Application Examples. - Programming. - What is RTL • What are Hardware Description Languages? - Concurrent Design - Verilog and VHDL - SystemVerilog • FPGA Architecture o Tech Docs/Specs: Look at FPGA’s Series_Overview.PDF file - CLBs, Slices, and LUTs - Resources Table - Clock Information - Block RAM, Registers - DSP Slices, XADC, Comm, I/O - Package Pin Number to Signal Mapping • Xilinx WebPack Vivado (takes over an hour to download and need to sign up for AMD account. • Quick Overview of EDA Playground (will only do a select set of): - Creating a Playground - Setting up a Playground - Entering Descriptive Code - Entering Display System Tasks - Simulating with Display Tasks - Simulating with EPWave • Verilog – Coding Elements - Wires and Registers - Number Representation: Logic Values - Number Representation: Integers - Logic Gates - The Basics - Higher-Level statements - Data Assignments - Multiplexers and Demultiplexers - case statements - if-else - Hardwired assign - Tri-State Buffers in Veriog - Tri-State Buffer Implementation in Verilog - Sequential Logic - Sequential Logic Example in Verilog - Blocking vs Nonblocking Assignments - Assignment example in EDA Playground - Blocking Results - Nonblocking Results - Nonintuitive Results • A Combinational System Example - Let's make a 4-bit Adder! - A Verilog Implementation - Simulating with Multiple Source Files - Simulation - Test Bench - Propagation Delays - Multiple Bit Signals in Modelsim - Design an ALU (optional) • A Sequential System Example - Let’s Make an Up/Down Counter - A Verilog Implementation - Simulation - Design a Digital Clock • Wrap up • Course Project Demonstration for Certificate of Completion